.TH E1432_SET_CLOCK_FREQ 3 E1432
.SH NAME
.nf
e1432_set_clock_freq \- Set sample clock frequency
e1432_get_clock_freq \- Get sample clock frequency
.fi
.IX e1432_set_clock_freq(3) 3
.IX e1432_get_clock_freq(3) 3
.SH SYNOPSIS
.cS
SHORTSIZ16 e1432_set_clock_freq(E1432ID hw, SHORTSIZ16 ID,
                                FLOATSIZ32 freq)
SHORTSIZ16 e1432_get_clock_freq(E1432ID hw, SHORTSIZ16 ID,
                                FLOATSIZ32 *freq)
.cE
.SH DESCRIPTION
\fIe1432_set_clock_freq\fR sets the fundamental sample clock frequency
used by all input and source channels specified by the \fID\fR.  The
substrate is capable of creating a wide variety of sample clock
frequencies; however, each input or source channel generally supports
only a limited range of frequencies.

This sample clock frequency is the clock frequency that is connected
to one of the VXI TTLTRG lines, if needed to synchronize several E1432
modules.  This clock frequency is normally, but not always, the
fundamental rate at which data is collected from the ADCs on the SCAs.

The clock frequency determines which measurement spans are available,
and must therefore be set before setting the span with
\fIe1432_set_span\fR.

This parameter is a "global" parameter.  It applies to an entire E1432
module rather than to one of its channels.  The \fIID\fR parameter is
used only to identify which module the function applies to, and all
channels in that module will report the same value for this parameter.

\fIhw\fR must be the result of a successful call to
\fIe1432_assign_channel_numbers\fR, and specifies the group of
hardware to talk to.

\fIID\fR is either the ID of a group of channels that was obtained with a
call to \fIe1432_create_channel_group\fR, or the ID of a single channel.

\fIfreq\fR is the clock frequency, in Hertz.

.B Internal Clock Source

The way the specified \fIfreq\fR is used depends on the setting of the
\fIe1432_set_clock_source\fR parameter.  The default clock source,
\fBE1432_CLOCK_SOURCE_INTERNAL\fR, means that this module is
generating the sample clock internally.  In this case, the clock
frequency must be one of the frequencies that the E1432 module can
generate.

For the E1432 51.2 kHz input SCA, the valid clock frequencies (in Hz)
that can be generated are:

40960 41938.6 44122.1 48000 49152 50000 51200 52400.9 61440 62500
64000 65536 66666.6 76800 78125 80000 81920 96000 98304 100000 102400

For the E1433 196 kHz input SCA, the valid clock frequencies (in Hz)
that can be generated are all of those listed above, plus the
following:

122880 125000 128000 133333.3 153600 156250 163840 192000 196608

Some of the above clock frequencies (40960, 49152, 51200, 65536) are
useful when frequency-domain measurements are being performed.  They
are useful because they give round numbers when divided by powers of
two.  Some of them (48000, 50000, 64000, 66666.6, 80000) are useful
when time-domain measurements are being performed.  They are useful
because their reciprocal is a round number, or perhaps because when
decimated by a power of two, their reciprocal is a round number.

Other frequencies in the list may have special applications.  For
example, 61440 Hz might be useful when doing frequency-domain
measurements involving 60Hz power line harmonics and sub-harmonics.

For the E1433 196 kHz input SCA, the clock is used directly by the
ADC, and the maximum valid span is clock_freq / 2.56.

For the E1432 51.2 kHz input SCA, the clock is used directly if it is
51200 Hz or less.  This means that the largest valid span will be
clock_freq / 2.56.  If the clock frequency is larger than 51200 Hz,
the clock is effectively divided by two before use.  This means that
the largest valid span will be clock_freq / 5.12.  See the manual page
for \fIe1432_set_span\fR for more details.

For the E1434 source, and the Option 1D4 source board, the valid clock
frequencies are the same as those for the E1432 51.2 kHz input SCA,
except that the maximum allowed clock frequency is 65536 Hz.

.B External Clock Sources

If the \fIe1432_set_clock_source\fR parameter is set to
\fBE1432_CLOCK_SOURCE_VXI\fR, \fBE1432_CLOCK_SOURCE_EXTERNAL\fR, or
\fBE1432_CLOCK_SOURCE_EXTERNALN\fR, it means that this module is not
generating the clock internally.  In this case, the clock frequency
coming into the module must still be within the range of 40960 Hz to
102400 Hz (for the E1432) or 40960 Hz to 196608 Hz (for the E1433), or
40960 Hz to 65536 Hz (for the E1434).  The \fIfreq\fR parameter to
\fIe1432_set_clock_freq\fR must match the frequency coming into the
module, and the frequency coming into the module must be a fixed
frequency so that the module's internal phase locked loop can lock to
the external clock.

The module will use the specified \fIfreq\fR to determine the valid
spans.  For the E1433 196 kHz input SCA, the clock is used directly by
the ADC, and the maximum valid span is clock_freq / 2.56.

For the E1432 51.2 kHz input SCA, the clock is used directly if it is
51200 Hz or less.  This means that the largest valid span will be
clock_freq / 2.56.  If the clock frequency is larger than 51200 Hz,
the clock is effectively divided by two before use.  This means that
the largest valid span will be clock_freq / 5.12.  The maximum allowed
clock frequency is 102400 Hz.  See the manual page for
\fIe1432_set_span\fR for more details.

For the Option 1D4 source board, the maximum valid clock frequency is
65536 Hz.

In multiple module E1432/E1433 systems, changing the clock frequency after
a measurement has been made without first resetting the measurement can
result in difficult to diagnose errors.
For this reason, it is advisable to precede each \fIe1432_set_clock_freq\fR
call in even potentially multimodule systems with with a
\fIe1432_reset_measure\fR call.

.SH "RESET VALUE"
The default clock frequency is 51200 Hz.
.SH "RETURN VALUE"
Return 0 if successful, a (negative) error number otherwise.
.SH "SEE ALSO"
.na
e1432_get_clock_freq_limits, e1432_set_span, e1432_set_clock_source
.ad
